The fabrication of semiconductor circuits generally and repeatedly performs a series of processes including lithography, deposition, etching, and the like to form layer-stacked integrated circuits. However, as the feature size of the semiconductor device shrinks, the processes become difficult to control and the precision of the process is highly demanded, so that the overlay precision of the photomasks and the alignment technology in the lithography process become more and more difficult to control.
The conventional methods of forming memory devices generally include performing the exposure and the development processes several times to independently define the active area, the floating gate pattern, and the control gate pattern, so as to adjust or increase the coupling area between the floating gate and the control gate. However, the conventional method increases the complexity of integration, and every additional photomask procedure raises the cost and increase the process time. Moreover, as described above, the alignment issue becomes more and more critical as the feature size shrinks and more photomasks are implemented.
Therefore, it is desired to provide a method of forming a semiconductor structure to reduce the required lithography steps by using a self-aligned manner to define the floating gate of the memory device.